NDLI: IATAC: a smart predictor to turn-off L2 cache lines

Please wait, while we are loading the content...

ACM Transactions on Architecture and Code Optimization (TACO) : Volume 13

ACM Transactions on Architecture and Code Optimization (TACO) : Volume 12

ACM Transactions on Architecture and Code Optimization (TACO) : Volume 11

ACM Transactions on Architecture and Code Optimization (TACO) : Volume 10

ACM Transactions on Architecture and Code Optimization (TACO) : Volume 9

ACM Transactions on Architecture and Code Optimization (TACO) : Volume 8

ACM Transactions on Architecture and Code Optimization (TACO) : Volume 7

ACM Transactions on Architecture and Code Optimization (TACO) : Volume 6

ACM Transactions on Architecture and Code Optimization (TACO) : Volume 5

ACM Transactions on Architecture and Code Optimization (TACO) : Volume 4

ACM Transactions on Architecture and Code Optimization (TACO) : Volume 3

ACM Transactions on Architecture and Code Optimization (TACO) : Volume 2

Issue 4, December 2005

Issue 3, September 2005

Issue 2, June 2005

Issue 1, March 2005

Introduction

Efficient and flexible architectural support for dynamic monitoring

A way-halting cache for low-energy high-performance systems

IATAC: a smart predictor to turn-off L2 cache lines

Accelerated warmup for sampled microarchitecture simulation

ACM Transactions on Architecture and Code Optimization (TACO) : Volume 1

IATAC: a smart predictor to turn-off L2 cache lines

Content Provider	ACM Digital Library
Author	González, Antonio Vera, Xavier O'boyle, Michael F. P. Abella, Jaume
Copyright Year	2005
Abstract	As technology evolves, power dissipation increases and cooling systems become more complex and expensive. There are two main sources of power dissipation in a processor: dynamic power and leakage. Dynamic power has been the most significant factor, but leakage will become increasingly significant in future. It is predicted that leakage will shortly be the most significant cost as it grows at about a 5× rate per generation. Thus, reducing leakage is essential for future processor design. Since large caches occupy most of the area, they are one of the leakiest structures in the chip and hence, a main source of energy consumption for future processors.This paper introduces $\textit{IATAC}$ (inter-access time per access count), a new hardware technique to reduce cache leakage for L2 caches. $\textit{IATAC}$ dynamically adapts the cache size to the program requirements turning off cache lines whose content is not likely to be reused. Our evaluation shows that this approach outperforms all previous state-of-the-art techniques. $\textit{IATAC}$ turns off 65% of the cache lines across different L2 cache configurations with a very small performance degradation of around 2%.
Starting Page	55
Ending Page	77
Page Count	23
File Format	PDF
ISSN	15443566
e-ISSN	15443973
DOI	10.1145/1061267.1061271
Volume Number	2
Issue Number	1
Journal	ACM Transactions on Architecture and Code Optimization (TACO)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-03-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Cache memories L2 cache Low power Turning off cache lines
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Information Systems Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A way-halting cache for low-energy high-performance systems

Dynamic access distance driven cache replacement

Reducing cache misses through programmable decoders

Performance Analysis of Cache Memories

Tiny instruction caches for low power embedded systems

Multicopy Cache: A Highly Energy-Efficient Cache Architecture

A highly configurable cache for low energy embedded systems

Spectral prefetcher: An effective mechanism for L2 cache prefetching

A self-tuning cache architecture for embedded systems

IATAC: a smart predictor to turn-off L2 cache lines

Similar Documents

A way-halting cache for low-energy high-performance systems

Dynamic access distance driven cache replacement

Reducing cache misses through programmable decoders

Performance Analysis of Cache Memories

Tiny instruction caches for low power embedded systems

Multicopy Cache: A Highly Energy-Efficient Cache Architecture

A highly configurable cache for low energy embedded systems

Spectral prefetcher: An effective mechanism for L2 cache prefetching

A self-tuning cache architecture for embedded systems

IATAC: a smart predictor to turn-off L2 cache lines