NDLI: A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration

Content Provider	ACM Digital Library
Author	Yang, Chia-Lin Li, Hsiang-Pang Lin, Ye-Jyun Wang, Cheng-Yuan Michael
Copyright Year	2016
Description	Author Affiliation: National Taiwan University(Wang, Cheng-Yuan Michael; Li, Hsiang-Pang; Macronix international co., Ltd. (Lin, Ye-Jyun; Yang, Chia-Lin))
Abstract	Flash memory is widely used in mobile phones to store contact information, application files, and other types of data. In an operating system, the buffer cache keeps the I/O blocks in dynamic random access memory (DRAM) to reduce the slow flash accesses. However, in smartphones, we observed two issues which reduce the benefits of the buffer cache. First, a large number of synchronous writes force writing the data from the buffer cache to flash frequently. Second, the large amount of I/O accesses from background applications diminishes the buffer cache efficiency of the foreground application, which degrades the quality-of-service (QoS). In this article, we propose a buffer cache architecture with hybrid DRAM and phase change memory (PCM) memory, which improves the I/O performance and QoS for smartphones. We use a DRAM first-level buffer cache to provide high buffer cache performance and a PCM last-level buffer cache to reduce the impact of frequent synchronous writes. Based on the proposed hierarchical buffer cache architecture, we propose a sub-block management and background flush to reduce the impact of the PCM write limitation and the dirty block write-back overhead, respectively. To improve the QoS, we propose a least-recently-activated first replacement policy (LRA) to keep the data from the applications that are most likely to become the foreground one. The experimental results show that with the proposed mechanisms, our hierarchical buffer cache can improve the I/O response time by 20% compared to the conventional buffer cache. The proposed LRA can improve the foreground application performance by 1.74x compared to the conventional CLOCK policy.
Starting Page	1
Ending Page	22
Page Count	22
File Format	PDF
ISSN	10844309
e-ISSN	15577309
DOI	10.1145/2979143
Volume Number	22
Issue Number	2
Journal	ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-12-28
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Buffer cache Phase change memory (PCM) Smartphone
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering

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