NDLI: Secure and Flexible Trace-Based Debugging of Systems-on-Chip

Content Provider	ACM Digital Library
Author	Karri, Ramesh Hely, David Backer, Jerry
Copyright Year	2016
Description	Author Affiliation: University of Grenoble Alpes(Karri, Ramesh; New york university, Brooklyn, NY (Backer, Jerry; Hely, David))
Abstract	This work tackles the conflict between enforcing security of a system-on-chip (SoC) and providing observability during trace-based debugging. On one hand, security objectives require that assets remain confidential at different stages of the SoC life cycle. On the other hand, the trace-based debug infrastructure exposes values of internal signals that can leak the assets to untrusted third parties. We propose a secure trace-based debug infrastructure to resolve this conflict. The secure infrastructure tags each asset to identify its owner (to whom it can be exposed during debug) and nonintrusively enforces the confidentiality of the assets during runtime debug. We implement a prototype of the enhanced infrastructure on an FPGA to validate its functional correctness. ASIC estimations show that our approach incurs practical area and power costs.
Starting Page	1
Ending Page	25
Page Count	25
File Format	PDF
ISSN	10844309
e-ISSN	15577309
DOI	10.1145/2994601
Volume Number	22
Issue Number	2
Journal	ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-12-28
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	System-on-chip Debug traces Secure debug
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An event-based monitoring service for networks on chip

Probabilistic system-on-a-chip architectures

A full lifecycle performance verification methodology for multicore systems-on-chip

A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains

Formal-Analysis-Based Trace Computation for Post-Silicon Debug

Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network

Computing Minimal Debugging Windows in Failure Traces of AMS Assertions

Optimal test access architectures for system-on-a-chip

On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems

Secure and Flexible Trace-Based Debugging of Systems-on-Chip

Similar Documents

An event-based monitoring service for networks on chip

Probabilistic system-on-a-chip architectures

A full lifecycle performance verification methodology for multicore systems-on-chip

A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains

Formal-Analysis-Based Trace Computation for Post-Silicon Debug

Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network

Computing Minimal Debugging Windows in Failure Traces of AMS Assertions

Optimal test access architectures for system-on-a-chip

On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems

Secure and Flexible Trace-Based Debugging of Systems-on-Chip