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| Content Provider | ACM Digital Library |
|---|---|
| Author | PĂĽschel, Markus Zuluaga, Marcela Milder, Peter |
| Copyright Year | 2016 |
| Abstract | Sorting is a fundamental problem in computer science and has been studied extensively. Thus, a large variety of sorting methods exist for both software and hardware implementations. For the latter, there is a trade-off between the throughput achieved and the cost (i.e., the logic and storage invested to sort $\textit{n}$ elements). Two popular solutions are bitonic sorting networks with $\textit{O}(\textit{n}log$ $^{2}n)$ logic and storage, which sort $\textit{n}$ elements per cycle, and linear sorters with $\textit{O}(\textit{n})$ logic and storage, which sort $\textit{n}$ elements per $\textit{n}$ cycles. In this article, we present new hardware structures that we call streaming sorting networks, which we derive through a mathematical formalism that we introduce, and an accompanying domain-specific hardware generator that translates our formal mathematical description into synthesizable RTL Verilog. With the new networks, we achieve novel and improved cost-performance trade-offs. For example, assuming that $\textit{n}$ is a two-power and $\textit{w}$ is any divisor of $\textit{n},$ one class of these networks can sort in $\textit{n}/;\textit{w}$ cycles with $\textit{O}(\textit{w}log$ $^{2}n)$ logic and $\textit{O}(\textit{n}log$ $^{2}n)$ storage; the other class that we present sorts in $\textit{n}log$ $^{2}n/;w$ cycles with $\textit{O}(\textit{w})$ logic and $\textit{O}(\textit{n})$ storage. We carefully analyze the performance of these networks and their cost at three levels of abstraction: (1) asymptotically, (2) exactly in terms of the number of basic elements needed, and (3) in terms of the resources required by the actual circuit when mapped to a field-programmable gate array. The accompanying hardware generator allows us to explore the entire design space, identify the Pareto-optimal solutions, and show superior cost-performance trade-offs compared to prior work. |
| Starting Page | 1 |
| Ending Page | 30 |
| Page Count | 30 |
| File Format | |
| ISSN | 10844309 |
| e-ISSN | 15577309 |
| DOI | 10.1145/2854150 |
| Volume Number | 21 |
| Issue Number | 4 |
| Journal | ACM Transactions on Design Automation of Electronic Systems (TODAES) |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2016-05-27 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | HDL generation Hardware sorting Design space exploration |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering |
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