NDLI: Clock buffer polarity assignment with skew tuning

Content Provider	ACM Digital Library
Author	Taskin, Baris Lu, Jianchao
Copyright Year	2011
Abstract	A clock polarity assignment method is proposed that reduces the peak current on the vdd/gnd rails of an integrated circuit. The impacts of (i) the output capacitive load on the peak current drawn by the sink-level clock buffers, and (ii) the buffer/inverter replacement scheme of polarity assignment on timing accuracy are considered in the formulation. The proposed sink-level-only polarity assignment is performed by a lexi-search algorithm in order to balance the peak current on the clock tree. Most of the previous polarity assignment methods that do not include clock tree resynthesis lead to an undesirable increase in the worst corner clock skew. Hence, a skew-tuning scheme is proposed that reduces the clock skew through polarity refinement and not through clock tree resynthesis. The proposed polarity assignment method with the skew-tuning scheme is implemented within an industrial design flow for practicality. Experimental results show that the worst-case peak current drawn by the clock tree can be reduced by an average of 36.5%. The worst corner clock skew is increased from 60.7ps to 76.2ps by applying the proposed polarity assignment method. The proposed skew-tuning scheme reduces the worst-case clock skew from 76.2ps to 61.5ps, on average, with a limited degradation in the peak current improvement (36.5% to 31.2%, on average).
Starting Page	1
Ending Page	22
Page Count	22
File Format	PDF
ISSN	10844309
e-ISSN	15577309
DOI	10.1145/2003695.2003709
Volume Number	16
Issue Number	4
Journal	ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-10-27
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Clock network synthesis Clock skew Physical design Polarity assignment
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Skew-aware polarity assignment in clock tree

Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization

A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems

Low-power gated and buffered clock network construction

Custom topology rotary clock router with tree subnetworks

Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs

Revisiting automated physical synthesis of high-performance clock networks

Low-power anti-aging zero skew clock gating

Skew aware polarity assignment in clock tree

Clock buffer polarity assignment with skew tuning

Similar Documents

Skew-aware polarity assignment in clock tree

Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization

A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems

Low-power gated and buffered clock network construction

Custom topology rotary clock router with tree subnetworks

Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs

Revisiting automated physical synthesis of high-performance clock networks

Low-power anti-aging zero skew clock gating

Skew aware polarity assignment in clock tree

Clock buffer polarity assignment with skew tuning