NDLI: Methods for power optimization in SOC-based data flow systems

Content Provider	ACM Digital Library
Author	Feautrier, Paul Grosse, Philippe Durand, Yves
Copyright Year	2009
Abstract	Whereas the computing power of DSP or general-purpose processors was sufficient for 3G baseband telecommunication algorithms, stringent timing constraints of 4G wireless telecommunication systems require computing-intensive data-driven architectures. Managing the complexity of these systems within the energy constraints of a mobile terminal is becoming a major challenge for designers. System-level low-power policies have been widely explored for generic software-based systems, but data-flow architectures used for high data-rate telecommunication systems feature heterogeneous components that require specific configurations for power management. In this study, we propose an innovative power optimization scheme tailored to self-synchronized data-flow systems. Our technique, based on the synchronous data-flow modeling approach, takes advantage of the latest low-power techniques available for digital architectures. We illustrate our optimization method on a complete 4G telecommunication baseband modem and show the energy savings expected by this technique considering present and future silicon technologies.
Starting Page	1
Ending Page	20
Page Count	20
File Format	PDF
ISSN	10844309
e-ISSN	15577309
DOI	10.1145/1529255.1529260
Volume Number	14
Issue Number	3
Journal	ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-06-04
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	4G base-band modem Power optimization Data-driven SOC Synchronous data-flow graph
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Runtime verification for multicore SoC with high-quality trace data

Postscheduling buffer management trade-offs in streaming software synthesis

Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers

Multiple wire reconnections based on implication flow graph

Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA

A Graph-Based Approach to Power-Constrained SOC Test Scheduling

Graph-based code selection techniques for embedded processors

A design automation and power estimation flow for RFID systems

Data-driven performance-based topology optimization of uncertain wind-excited tall buildings

Methods for power optimization in SOC-based data flow systems

Similar Documents

Runtime verification for multicore SoC with high-quality trace data

Postscheduling buffer management trade-offs in streaming software synthesis

Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers

Multiple wire reconnections based on implication flow graph

Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA

A Graph-Based Approach to Power-Constrained SOC Test Scheduling

Graph-based code selection techniques for embedded processors

A design automation and power estimation flow for RFID systems

Data-driven performance-based topology optimization of uncertain wind-excited tall buildings

Methods for power optimization in SOC-based data flow systems