NDLI: A speed FPGA hardware accelerator based FSBMA-VBSME used in H.264/AVC

Please wait, while we are loading the content...

A speed FPGA hardware accelerator based FSBMA-VBSME used in H.264/AVC

Content Provider	Springer Nature Link
Author	Yahi, Amira Toumi, Salah Bourennane, El bay Messaoudi, Kamel
Copyright Year	2015
Abstract	Image and video processing applications represent major challenge concerning real-time embedded systems. In video coding, adjacent frames are similar; this correlation can be exploited to reduce the amount of data to be transmitted, in this case reducing temporal redundancies. Actually, H.264/AVC is the most popular standard; the high performance that offers magnifies the difficulty of a real-time implementation. This complexity is mainly related to the operation of the motion estimation and requires high computational power. This paper presents an efficient hardware implementation of integer motion estimation for H.264/AVC encoder. The considered methodology is based on full search block matching algorithm for its regular algorithm implementation. The proposed architecture enables variable block size motion estimation and computes 41 motion vectors values (MVs) resulted from each 16 × 16 bloc and its derived sub-blocks. The proposed architecture calculates the best MV using a parallel process composed of three processor modules and a set of comparators three values. Implementation results based on field-programmable gate arrays devices uses Xilinx Virtex7 XC7VX550T show performance characteristics like low latency reduced up to 80 %, high processing speed reaching 443 MHz of frequency. The processing capacity is up to 1920 × 1088 HD video streams with a search range of 48 × 48.
Starting Page	233
Ending Page	241
Page Count	9
File Format	PDF
ISSN	18686478
Journal	Evolving Systems
Volume Number	7
Issue Number	4
e-ISSN	18686486
Language	English
Publisher	Springer Berlin Heidelberg
Publisher Date	2015-10-22
Publisher Place	Berlin, Heidelberg
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Video compression H.264/AVC Full search block matching algorithm Hardware implementation Parallel processors Complexity Artificial Intelligence (incl. Robotics) Complex Systems
Content Type	Text
Resource Type	Article
Subject	Control and Optimization Control and Systems Engineering Modeling and Simulation Computer Science Applications

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A High-Performance Architecture of the Double-Mode Binary Coder for H.264.AVC

Optimization of multimedia applications on embedded multicore processors

A novel VLSI architecture for full-search variable block-size motion estimation

A hierarchical design methodology for full-search block matching motion estimation

A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC

Intra Prediction for the Hardware H.264/AVC High Profile Encoder

Predictive and distribution-oriented fast motion estimation for H.264/AVC

Efficient Software H.264/AVC to HEVC Transcoding on Distributed Multicore Processors

Low-complexity transcoding algorithm from H.264/AVC to SVC using data mining

A speed FPGA hardware accelerator based FSBMA-VBSME used in H.264/AVC

Similar Documents

A High-Performance Architecture of the Double-Mode Binary Coder for H.264.AVC

Optimization of multimedia applications on embedded multicore processors

A novel VLSI architecture for full-search variable block-size motion estimation

A hierarchical design methodology for full-search block matching motion estimation

A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC

Intra Prediction for the Hardware H.264/AVC High Profile Encoder

Predictive and distribution-oriented fast motion estimation for H.264/AVC

Efficient Software H.264/AVC to HEVC Transcoding on Distributed Multicore Processors

Low-complexity transcoding algorithm from H.264/AVC to SVC using data mining

A speed FPGA hardware accelerator based FSBMA-VBSME used in H.264/AVC