NDLI: Scalable row-based parallel H.264 decoder on embedded multicore processors

Content Provider	Springer Nature Link
Author	Baaklini, Elias Rethinagiri, Santhosh Sbeity, Hassan Niar, Smail
Copyright Year	2014
Abstract	Multimedia applications are present in most mobile hand-held devices, which are still equipped with limited battery resources. The H.264 standard is currently dominating the video compression world. H.264 has high computational requirements in terms of memory, energy, and time. Many techniques emerged that optimize parallel task granularity on multicore systems ranging from groups of pictures until the smallest block of pixels. A scalable parallel technique for the motion compensation phase is proposed in this research that is based on processing of groups of macroblock rows. Moreover, a light dependency detection algorithm is added to the prediction phase that enables parallel execution and minimizes synchronization stall time. Furthermore, a parallel implementation of the deblocking filter is also implemented. The overall result is an efficient and highly scalable parallel H.264 decoder that is evaluated on a real-board platform composed of an ARM Cortex-A9 MPCore with four processors. Various low- and high-definition video sequences are used in experiments. Results show that execution time reaches a speedup of 3.3 $$\times $$ for motion compensation stage and an overall speedup of 2.3 $$\times $$ on 4 cores including communication and synchronization overhead. Energy consumption decreases up to 63 % for the whole application execution.
Starting Page	57
Ending Page	71
Page Count	15
File Format	PDF
ISSN	18631703
Journal	Signal, Image and Video Processing
Volume Number	9
Issue Number	1
e-ISSN	18631711
Language	English
Publisher	Springer London
Publisher Date	2014-03-21
Publisher Place	London
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Multimedia H.264/AVC standard Video compression Optimization Parallel computing Embedded systems Multicore processors Signal, Image and Speech Processing Image Processing and Computer Vision Computer Imaging, Vision, Pattern Recognition and Graphics Multimedia Information Systems
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Optimization of multimedia applications on embedded multicore processors

Real-time H.264/AVC baseline decoder implementation on TMS320C6416

A scalable H.264/AVC deblocking filter architecture

A receiver aware H.264/AVC encoder for decoder complexity control in mobile applications

Low-complexity quantization for H.264/AVC

A real-time H.264/AVC VLSI encoder architecture

Wireless transmission of HD video using H.264 compression over UWB channel

Low-complexity heterogeneous architecture for H.264/HEVC video transcoding

A fast rate-distortion optimization algorithm for H.264/AVC codec

Scalable row-based parallel H.264 decoder on embedded multicore processors

Similar Documents

Optimization of multimedia applications on embedded multicore processors

Real-time H.264/AVC baseline decoder implementation on TMS320C6416

A scalable H.264/AVC deblocking filter architecture

A receiver aware H.264/AVC encoder for decoder complexity control in mobile applications

Low-complexity quantization for H.264/AVC

A real-time H.264/AVC VLSI encoder architecture

Wireless transmission of HD video using H.264 compression over UWB channel

Low-complexity heterogeneous architecture for H.264/HEVC video transcoding

A fast rate-distortion optimization algorithm for H.264/AVC codec

Scalable row-based parallel H.264 decoder on embedded multicore processors