NDLI: An Error Recoverable Structure Based on Complementary Logic and Alternating-Retry

Content Provider	Springer Nature Link
Author	Jiang, Jian Hui
Copyright Year	2005
Abstract	Modern VLSI circuits provide adequate on-chip resources. So that online testing and retry integrated into a chip are absolutely necessary for system-on-a-chip technology. This paper firstly proposes a general online testing plus retrying structure. Obviously, although retry can mask transient or intermittent faults, it is useless for handling permanent faults generally. To solve this problem, this paper presents a novel dual modular redundancy (DMR) structure using complementary logic—alternating-complementary logic (CL-ACL) switching mode. During error-free operation, the CL-ACL structure operates by complementary logic mode. After an error is detected, it retries by alternating logic mode. If all errors belong to single or multiple temporary 0/1-error or stuck-at-error produced by one module, then these errors can be corrected effectively. The results obtained from the simulation validate the correctness of the CL-ACL structure. Analytic results show that the delay of the CL-ACL structure is dramatically less than that of a DMR structure using alternating-complementary logic mode.
Starting Page	885
Ending Page	894
Page Count	10
File Format	PDF
ISSN	10009000
Journal	Journal of Computer Science and Technology
Volume Number	20
Issue Number	6
e-ISSN	18604749
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2005-01-01
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	error recovery fault tolerance complementary logic alternating-retry temporary error stuck-at-error Theory of Computation Information Systems Applications (incl.Internet) Artificial Intelligence (incl. Robotics) Computer Science Software Engineering Data Structures, Cryptology and Information Theory
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Computer Science Applications Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Fault Tolerance and Recovery for Group Communication Services in Distributed Networks

I $_{DDT}$: Fundamentals and test generation

Fault-tolerant grid architecture and practice

Fault tolerance of reconfigurable bi-directional double-loop LANs

On fault tolerance of 3-dimensional mesh networks

A new classification of path-delay fault testability in terms of stuck-at faults

Fault-tolerant systems with concurrent error-locating capability

Hybrid Nanoelectronics: Future of Computer Technology

SFT: A consistent checkpointing algorithm with short freezing time

An Error Recoverable Structure Based on Complementary Logic and Alternating-Retry

Similar Documents

Fault Tolerance and Recovery for Group Communication Services in Distributed Networks

I $_{DDT}$: Fundamentals and test generation

Fault-tolerant grid architecture and practice

Fault tolerance of reconfigurable bi-directional double-loop LANs

On fault tolerance of 3-dimensional mesh networks

A new classification of path-delay fault testability in terms of stuck-at faults

Fault-tolerant systems with concurrent error-locating capability

Hybrid Nanoelectronics: Future of Computer Technology

SFT: A consistent checkpointing algorithm with short freezing time

An Error Recoverable Structure Based on Complementary Logic and Alternating-Retry