NDLI: I $_{DDT}$: Fundamentals and test generation

Content Provider	Springer Nature Link
Author	Kuang, Jishun You, ZhiQiang Zhu, QiJian Min, YingHua
Copyright Year	2003
Abstract	It is the time to explore the fundamentals ofI $_{DDT}$ testing when extensive work has been done forI $_{DDT}$ testing since it was proposed. This paper precisely defines the concept of average transient current (I $_{DDT}$) of CMOS digital ICs, and experimentally analyzes the feasibility ofI $_{DDT}$ test generation at gate level. Based on the SPICE simulation results, the paper suggests a formula to calculateI $_{DDT}$ by means of counting only logical up-transitions, which enablesI $_{DDT}$ test generation at logic level. The Bayesian optimization algorithm is utilized forI $_{DDT}$ test generation. Experimental results show that about 25% stuck-open faults are withI $_{DDT}$ test generation. 2.5, and likely to beI $_{DDT}$ testable. It is also found that mostI $_{DDT}$ testable faults are located near the primary inputs of a circuit under test.I $_{DDT}$ test generation does not require fault sensitization procedure compared with stuck-at fault test generation. Furthermore, some redundant stuck-at faults can be detected by usingI $_{DDT}$ testing.
Starting Page	299
Ending Page	307
Page Count	9
File Format	PDF
ISSN	10009000
Journal	Journal of Computer Science and Technology
Volume Number	18
Issue Number	3
e-ISSN	18604749
Language	English
Publisher	Science Press
Publisher Date	2003-01-01
Publisher Place	Beijing
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	I $_{DDT}$ testing logical transition hazard stuck-open fault Computer Science Software Engineering Theory of Computation Data Structures, Cryptology and Information Theory Artificial Intelligence (incl. Robotics) Information Systems Applications (incl.Internet)
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Computer Science Applications Software Hardware and Architecture

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