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| Content Provider | Springer Nature Link |
|---|---|
| Author | Chung, Rih Lung Hwang, Jeng Kuang |
| Copyright Year | 2006 |
| Abstract | This paper investigates an inherent but adverse phenomenon called cyclic intersymbol interference (cyclic ISI) occurred in frequency-domain decision-feedback equalizer (FD-DFE). The cyclic ISI is due to the cyclic-prefix insertion and modulo operation of the time-domain feedback filter. To analyze and further mitigate this problem, we first formulate the FD-DFE signal model in a compact and insightful vector-matrix form, which allows an efficient derivation of the MMSE receiver coefficients. Then, by viewing the bit-error-rate profile (BERP) with respect to different starting symbol position within a symbol block, it is shown that those leading data symbols suffer more from the cyclic-ISI effect and lead to a high error floor. Seeing this, a novel FD-DFE receiver structure, called P2B-FD-DFE (parallel-two-branch FD-DFE) receiver, is proposed to overcome this problem without sacrificing spectral efficiency. It consists of two parallel cooperating branches of almost identical FD-DFE receivers designed for different cyclic decision delays. Under severe cyclic-ISI circumstances, the receiver performance can be further improved by using (1) a larger block size, and/or (2) a cascade of multiple feedback stages. Simulation results demonstrate that, in severe ISI channel, while the conventional FD-DFE exhibits a very high error floor, our proposed receiver can almost completely suppress the cyclic-ISI effect. |
| Starting Page | 327 |
| Ending Page | 341 |
| Page Count | 15 |
| File Format | |
| ISSN | 09296212 |
| Journal | Wireless Personal Communications |
| Volume Number | 39 |
| Issue Number | 3 |
| e-ISSN | 1572834X |
| Language | English |
| Publisher | Kluwer Academic Publishers-Plenum Publishers |
| Publisher Date | 2006-09-23 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | block transmission cyclic intersymbol interference (cyclic ISI) frequency-domain decision-feedback equalizer (FD-DFE) cyclic decision delay Processor Architectures Signal, Image and Speech Processing Electronic and Computer Engineering |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Computer Science Applications |
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