NDLI: MMSE Equalizer for MIMO-ISI Channel With Shorten Guard Period

Content Provider	IEEE Xplore Digital Library
Author	Man-Wai Kwan Kok, C.-W.
Copyright Year	1991
Abstract	A finite-impulse-response minimum mean-square error equalizer (FIR-MMSEE) for block-based transmission over a multiple-input multiple-output (MIMO) intersymbol interference (ISI) channels is proposed in this correspondence. The proposed MMSE equalizer can avoid interblock interference (IBI) without requiring a guard period to be larger than or equal to the channel order. By reducing the number of redundant symbols in the transmitted signals, the spectral efficiency of the communication system with long channel dispersion can be greatly improved. We further investigated the parallel FIR-MMSEE equalization structure and proposed a group successive interference cancellation MMSE equalizer (GSIC-MMSEE). A group of elements in the output of the FIR-MMSEE will be used to successively cancel their own effect in the received signals after the signal detection in GSIC-MMSEE. Since the cancellation process eliminates some interference sources, the error performance of the subsequent equalization will be improved. Moreover, the interference cancellation is performed in a group-by-group basis. As a result, the computational complexity of the proposed equalizer can be controlled by adjusting the number of groups in the GSIC. Simulation results are presented to compare the performance of the proposed FIR-MMSEE and GSIC-MMSEE
Sponsorship	IEEE Signal Processing Society
Starting Page	389
Ending Page	395
Page Count	7
File Size	414394
File Format	PDF
ISSN	1053587X
Volume Number	55
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Equalizers MIMO Intersymbol interference Interference cancellation Signal resolution Frequency-selective fading channels Signal detection Computational complexity Block codes Wireless communication successive interference cancellation Decision feedback equalizer filter bank MMSE equalizer multiple antenna multiple-input multiple-output (MIMO) precoder– equalizer space–time block code (STBC) space–time modulated code (STMC)
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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