NDLI: Low-Power High-Speed Hybrid Wave-Pipeline Architectures for Binary Morphological Dilation

Content Provider	Springer Nature Link
Author	Hajirahimi, Mahdiye Nabavi, Abdolreza Kabir, Ehsalah
Copyright Year	2011
Abstract	Dilation and erosion are two fundamental operations of mathematical morphology for image processing. This paper presents three hybrid wave-pipeline (HWP) architectures for real-time binary dilation operator. With minor changes to the number and/or to the type of the basic gates, they can be employed as erosion operator. In the first HWP-architecture, each single cell utilizes the wave technique along with delay units for balancing the data paths. By minimizing the number of delay units, the second HWP-architecture with reduced power consumption and hardware complexity is obtained. The third HWP-architecture employs wave technique in each three cascaded cells. This architecture improves the above performance further, at the cost of slight reduction in maximum clock frequency and clock frequency range. Simulation results, using a 0.18 μm CMOS technology, indicate that the HWP architectures have higher speed, less hardware complexity, and lower power consumption compared to pipeline (P) architecture. Also, they are faster than wave-pipeline (WP) architecture, without the difficulty of balancing the delay of long signal paths. Simulation illustrates that the third HWP-architecture dilates a 1024 × 1024 image by a 21 × 21 structuring element (SE) in 214.64 μs. The maximum frequency of operation is 5 GHz for the power supply of 1.8 V. The power dissipation is 410 mW, and the chip area is 0.075 mm$^{2}$.
Starting Page	391
Ending Page	399
Page Count	9
File Format	PDF
ISSN	19398018
Journal	Journal of Signal Processing Systems
Volume Number	68
Issue Number	3
e-ISSN	19398115
Language	English
Publisher	Springer US
Publisher Date	2011-10-13
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Real time image processing Morphology Dilation Binary image ASIC CMOS Hybrid wave pipeline Signal, Image and Speech Processing Computer Imaging, Vision, Pattern Recognition and Graphics Pattern Recognition Electrical Engineering Circuits and Systems Image Processing and Computer Vision
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Signal Processing Control and Systems Engineering Information Systems Modeling and Simulation Hardware and Architecture

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