NDLI: Full-Hardware Architectures for Data-Dependent Superimposed Training Channel Estimation

Content Provider	Springer Nature Link
Author	Romero Aguirre, Eduardo Carrasco Alvarez, Roberto Parra Michel, Ramón Orozco Lugo, Aldo G. Mondragón Torres, Antonio F.
Copyright Year	2012
Abstract	Channel estimation based on superimposed training (ST) has been an active research topic around the world in recent years, because it offers similar performance when compared to methods based on pilot assisted transmissions (PAT), with the advantage of a better bandwidth utilization. However, physical implementations of such estimators are still under research, and only few approaches have been reported to date. This is due to the computational burden and complexity involved in the algorithms in conjunction with their relative novelty. In order to determine the suitability of the ST-based channel estimation for commercial applications, the performance and complexity analysis of the ST approaches is mandatory. This work proposes two full-hardware channel estimator architectures for a data-dependent superimposed training (DDST) receiver with perfect synchronization and nonexistent DC-offset. These architectures were described using Verilog HDL and targeted in Xilinx Virtex-5 XC5VLX110T FPGA. The synthesis results of such estimators showed a consumption of 3 % and 1 % of total slices available in the FPGA and frequencies operation over 160 MHz. They have also been implemented on a generic 90 nm CMOS process achieving clock frequencies of 187 MHz and 247 MHz while consuming 3.7 mW and 2.74 mW, respectively. In addition, for the first time, a novel architecture that includes channel estimation, training/block synchronization and DC-offset estimation is also proposed. Its fixed-point analysis has been carried out, allowing the design to produce practically equal performance to those achieved with the floating-point models. Finally, the high throughputs and reduced hardware consumptions of the implemented channel estimators, leads to the conclusion that ST/DDST can be utilized in practical communications systems.
Starting Page	105
Ending Page	123
Page Count	19
File Format	PDF
ISSN	19398018
Journal	Journal of Signal Processing Systems
Volume Number	70
Issue Number	2
e-ISSN	19398115
Language	English
Publisher	Springer US
Publisher Date	2012-10-24
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Channel estimation Data-dependent superimposed training FPGA architectures Implicit training Synchronization VLSI Signal, Image and Speech Processing Circuits and Systems Electrical Engineering Image Processing and Computer Vision Pattern Recognition Computer Imaging, Vision, Pattern Recognition and Graphics
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Signal Processing Control and Systems Engineering Information Systems Modeling and Simulation Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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