NDLI: Scalable Parallel Memory Architectures for Video Coding

Content Provider	Springer Nature Link
Author	Tanskanen, Jar K. Niittylahti, Jarkko T.
Copyright Year	2004
Abstract	Current video compression standards, which process frames macroblock by macroblock, employ several processing functions to achieve the compression. These functions refer to data memory address space in different ways. E.g., performing motion estimation and motion compensation functions requires many times data accesses unaligned to word boundaries. On the other hand, Discrete Cosine Transformation (DCT) and inverse of it (IDCT) for 8 × 8 block can be performed first for rows and then for columns. Thus, transposition is needed between these two stages. Among other things, parallel memory architecture can provide a solution for these tasks. In our other paper, we shortly surveyed parallel memory architectures and proposed parallel memory architecture designs for different data path widths for video coding applications. In this paper, we construct video coding function examples by using the proposed parallel data memory efficiently. Furthermore, performance and implementation cost of the parallel memory architecture are estimated and compared to more conventional memory architectures. The examples are given for different data bus widths (16, 32, 64, and 128 bits). We show that the parallel memory can keep the data path fully utilized in many video coding function implementations. This ensures high-speed operation and full utilization of the processing resources.
Starting Page	173
Ending Page	199
Page Count	27
File Format	PDF
ISSN	09225773
Journal	Journal of Signal Processing Systems
Volume Number	38
Issue Number	2
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2004-11-01
Publisher Place	Boston
Access Restriction	Subscribed
Subject Keyword	Signal, Image and Speech Processing Circuits and Systems Electrical Engineering Image Processing and Computer Vision Pattern Recognition Computer Imaging, Vision, Pattern Recognition and Graphics
Content Type	Text
Resource Type	Article
Subject	Signal Processing Information Systems Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Performance-Scalable Array Architectures for Modular Multiplication

Interleaving on Parallel DSP Architectures

Quadtree Optimization for Image and Video Coding

Motion Estimation for Video Coding Standards

Improved Update Step for Scalable Video Coding in Video Surveillance

A Parallel ASIC Architecture for Efficient Fractal Image Coding

A Parallel VLSI Video/Communication Controller

Scalable Architecture for SoC Video Encoders

On Design of Parallel Memory Access Schemes for Video Coding

Scalable Parallel Memory Architectures for Video Coding

Similar Documents

Performance-Scalable Array Architectures for Modular Multiplication

Interleaving on Parallel DSP Architectures

Quadtree Optimization for Image and Video Coding

Motion Estimation for Video Coding Standards

Improved Update Step for Scalable Video Coding in Video Surveillance

A Parallel ASIC Architecture for Efficient Fractal Image Coding

A Parallel VLSI Video/Communication Controller

Scalable Architecture for SoC Video Encoders

On Design of Parallel Memory Access Schemes for Video Coding

Scalable Parallel Memory Architectures for Video Coding