NDLI: Contention resolution mechanisms for asynchronous optical packet switching based high performance computing system

Content Provider	Springer Nature Link
Author	Zhao, Jun Sun, Xiaohan
Copyright Year	2009
Abstract	We propose an asynchronous optical packet switching (AOPS) based multistage interconnection network employing the distributed control and banyan-like routing scheme, which can construct the high performance computing system (HPCS). A flexible, low latency, and high capacity recycling-fiber-delay-line (Rec-FDL) based collision resolution mechanism is proposed with higher switching efficiency for burst services than that by the conventional packet retransmission algorithm (C-PRA). The system performances, including stability, blocking rate (BR), and longest packets waiting latency (LPWL) are analyzed. The simulation shows that the system stability condition for the Rec-FDL mechanism is the new packet arriving rate λ less than 30×10$^{6}$ packets/s. In addition, the BR and Rec-FDL induced LPWL are 0.1235–0.1413 and 6.305 ns–7.651 ns, respectively, with increasing the number of CPUs connected to the system from 4 to 16,384, while the increment for LPWL induced by the conventional algorithm is 3.9 ns at the same conditions as above. Therefore, the mechanism presented here is more beneficial for the system scalability and has higher latency reducing abilities than the C-PRA.
Starting Page	464
Ending Page	474
Page Count	11
File Format	PDF
ISSN	09208542
Journal	The Journal of Supercomputing
Volume Number	53
Issue Number	3
e-ISSN	15730484
Language	English
Publisher	Springer US
Publisher Date	2009-09-04
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	High performance computing system Asynchronous optical packet switching Collision resolution mechanism Stability Blocking rate Latency Computer Science Processor Architectures Programming Languages, Compilers, Interpreters
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Information Systems Hardware and Architecture Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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