NDLI: A fast placement algorithm for embedded just-in-time reconfigurable extensible processing platform

Content Provider	Springer Nature Link
Author	Daryanavard, H. Eshghi, M. Jahanian, A.
Copyright Year	2014
Abstract	Reasonable trade-off between the ASIC performance and GPP flexibility is the main objective of reconfigurable computing systems. Dynamic Reconfigurable computing platform using embedded just-in-time (JIT) compilation is the most flexible platform among others. All complex computing kernels can be translated to bitstream to be executed on FPGA using an embedded processor of dedicated specialized hardware. The main challenge in these systems is FPGA design automation time. Executing the CAD algorithms on embedded processor is too time-consuming and normally is not feasible for real applications. Placement is the most computative part of CAD algorithm. Therefore, a new FPGA placement algorithm is proposed in this paper which makes reasonable trade-off between execution time and quality of placement. The proposed algorithm includes two stages: force-directed placement and simulated annealing placement. The proposed algorithm is very low execution time to be useful in JIT compilation without considerable degradation on the quality of placement. Experimental results show $$2.33\times $$ speedup in execution time in cost of 3 % overhead in channel tracks numbers.
Starting Page	121
Ending Page	143
Page Count	23
File Format	PDF
ISSN	09208542
Journal	The Journal of Supercomputing
Volume Number	71
Issue Number	1
e-ISSN	15730484
Language	English
Publisher	Springer US
Publisher Date	2014-09-12
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	FPGA placement Just-in-time compilation Extensible processor Force directed Simulated annealing Programming Languages, Compilers, Interpreters Processor Architectures Computer Science
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Information Systems Hardware and Architecture Software

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