NDLI: Formalization and configuration methodology for high-radix combined switches

Content Provider	Springer Nature Link
Author	Villar, Juan A. Andújar, Francisco J. Alfaro, Francisco J. Sánchez, José L. Duato, José
Copyright Year	2014
Abstract	In large switch-based interconnection networks, increasing the switch radix results in a decrease in the total number of network components, and consequently the overall cost of the network can be significantly reduced. Moreover, high-radix switches are an attractive option to improve the network performance in terms of latency since hop count is also reduced. However, there are some difficulties related to integration scale to design such switches. In this paper we present and formalize an interesting alternative for building high-radix switches going beyond the integration scale bounds. The idea basically consists in combining several current smaller switches to obtain switches having greater number of ports. This strategy will remain valid as the scale of integration keeps evolving. Although simple, this strategy raises key design challenges in order to these high-radix switches achieve the best performance. The resultant internal structure of these switches becomes an important design decision, and an arbitrary selection may produce a significant performance degradation. For this reason, we also propose a general methodology to configure in an optimal way the internal switch structure and apply it to a particular case in order to show how it works. The resultant switch configurations are evaluated in order to show the real potential of our proposal.
Starting Page	1410
Ending Page	1444
Page Count	35
File Format	PDF
ISSN	09208542
Journal	The Journal of Supercomputing
Volume Number	69
Issue Number	3
e-ISSN	15730484
Language	English
Publisher	Springer US
Publisher Date	2014-06-17
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Network architecture and design Configuration methodology Formal analysis High-radix switches Fat-tree topology Performance evaluation Programming Languages, Compilers, Interpreters Processor Architectures Computer Science
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Information Systems Hardware and Architecture Software

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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