NDLI: Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs

Content Provider	Springer Nature Link
Author	Sterpone, L. Sonza Reorda, M. Violante, M. Kastensmidt, F. Lima Carro, L.
Copyright Year	2007
Abstract	The latest SRAM-based FPGA devices are making the development of low-cost, high-performance, re-configurable systems feasible, paving the way for innovative architectures suitable for mission- or safety-critical applications, such as those dominating the space or avionic fields. Unfortunately, SRAM-based FPGAs are extremely sensitive to Single Event Upsets (SEUs) induced by radiation. SEUs may alter the logic value stored in the memory elements the FPGAs embed. A large part of the FPGA memory elements is dedicated to the configuration memory, whose content dictates how the resources inside the FPGA have to be used to implement any given user circuit, SEUs affecting configuration memory cells can be extremely critics. Facing the effects of SEUs through radiation-hardened FPGAs is not cost-effective. Therefore, various fault-tolerant design techniques have been devised for developing dependable solutions, starting from Commercial-Off-The-Shelf (COTS) SRAM-based FPGAs. These techniques present advantages and disadvantages that must be evaluated carefully to exploit them successfully. In this paper we mainly adopted an empirical analysis approach. We evaluated the reliability of a multiplier, a digital FIR filter, and an 8051 microprocessor implemented in SRAM-based FPGA’s, by means of extensive fault-injection experiments, assessing the capability provided by different design techniques of tolerating SEUs within the FPGA configuration memory. Experimental results demonstrate that by combining architecture-level solutions (based on redundancy) with layout-level solutions (based on reliability-oriented place and route) designers may implement reliable re-configurable systems choosing the best solution that minimizes the penalty in terms of area and speed degradation.
Starting Page	47
Ending Page	54
Page Count	8
File Format	PDF
ISSN	09238174
Journal	Journal of Electronic Testing
Volume Number	23
Issue Number	1
e-ISSN	15730727
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2007-01-24
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	reliability SEU SRAM-based FPGA fault tolerant systems Circuits and Systems Electronic and Computer Engineering Computer-Aided Engineering (CAD, CAE) and Design
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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