NDLI: An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation

Content Provider	Springer Nature Link
Author	Shen, Jian Abraham, Jacob A.
Copyright Year	2000
Abstract	Design validation is becoming more and more a bottleneck in the microprocessor design process. The difficulty of validation stems from the complexity of the design, which requires searching an enormous space to check correctness. This is exacerbated by features for enhancing performance, such as pipelines, which are becoming common in most microprocessors. This paper describes a new abstraction technique to handle this problem. Our solution is a novel method to identify the control states automatically from the processor HDL description and to extract an abstract finite state machine model which preserves the behaviors of the design accurate to the clock cycle, so that the state space to be analyzed is drastically reduced.This model is used to evaluate microarchitecture-level coverage of validation tests. We also present validation test generation algorithm for traversing state transition paths and covering snapshot and temporal events. These abstract paths with a finite length, along with information about the instruction set, are used to generate system-level tests. Results on example microprocessor models show the technique is efficient in finding bugs that other verification methods miss.
Starting Page	67
Ending Page	81
Page Count	15
File Format	PDF
ISSN	09238174
Journal	Journal of Electronic Testing
Volume Number	16
Issue Number	1-2
e-ISSN	15730727
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2000-01-01
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Computer-Aided Engineering (CAD, CAE) and Design Electronic and Computer Engineering Circuits and Systems
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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