NDLI: Logic Design Validation via Simulation and Automatic Test Pattern Generation

Content Provider	Springer Nature Link
Author	Al asaad, Hussain Hayes, John P.
Copyright Year	2000
Abstract	We investigate an automated design validation scheme for gate-level combinational and sequential circuits that borrows methods from simulation and test generation for physical faults, and verifies a circuit with respect to a modeled set of design errors. The error models used in prior research are examined and reduced to five types: gate substitution errors (GSEs), gate count errors (GCEs), input count errors (ICEs), wrong input errors (WIEs), and latch count errors (LCEs). Conditions are derived for a gate to be testable for GSEs, which lead to small, complete test sets for GSEs; near-minimal test sets are also derived for GCEs. We analyze undetectability in design errors and relate it to single stuck-line (SSL) redundancy. We show how to map all the foregoing error types into SSL faults, and describe an extensive set of experiments to evaluate the proposed method. These experiments demonstrate that high coverage of the modeled errors can be achieved with small test sets obtained with standard test generation and simulation tools for physical faults.
Starting Page	575
Ending Page	589
Page Count	15
File Format	PDF
ISSN	09238174
Journal	Journal of Electronic Testing
Volume Number	16
Issue Number	6
e-ISSN	15730727
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2000-01-01
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Computer-Aided Engineering (CAD, CAE) and Design Electronic and Computer Engineering Circuits and Systems
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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