NDLI: The ArchC Architecture Description Language and Tools

Content Provider	Springer Nature Link
Author	Azevedo, Rodolfo Rigo, Sandro Bartholomeu, Marcus Araujo, Guido Araujo, Cristia Barros, Edna
Copyright Year	2005
Abstract	This paper presents an architecture description language (ADL) called ArchC, which is an open-source SystemC-based language that is specialized for processor architecture description. Its main goal is to provide enough information, at the right level of abstraction, in order to allow users to explore and verify new architectures, by automatically generating software tools like simulators and co-verification interfaces. ArchC’s key features are a storage-based co-verification mechanism that automatically checks the consistency of a refined ArchC model against a reference (functional) description, memory hierarchy modeling capability, the possibility of integration with other SystemC IPs and the automatic generation of high-level SystemC simulators and assemblers. We have used ArchC to synthesize both functional and cycle-based simulators for the MIPS and Intel 8051 processors, as well as functional models of architectures like SPARC V8, TMS320C62x, XScale and PowerPC.
Starting Page	453
Ending Page	484
Page Count	32
File Format	PDF
ISSN	08857458
Journal	International Journal of Parallel Programming
Volume Number	33
Issue Number	5
e-ISSN	15737640
Language	English
Publisher	Kluwer Academic Publishers-Plenum Publishers
Publisher Date	2005-01-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Architecture description language SystemC ISA simulator compiled simulation Processor Architectures Software Engineering/Programming and Operating Systems Theory of Computation
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Information Systems Software

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