NDLI: Formal Verification of a Complex Pipelined Processor

Content Provider	Springer Nature Link
Author	Hosabettu, Ravi Gopalakrishnan, Ganesh Srivas, Mandayam
Copyright Year	2003
Abstract	This paper addresses the problem of formally verifying the correctness of a complex pipelined microprocessor at the micro-architectural level of abstraction. The design verified is an example out-of-order execution processor with a reorder buffer, a store buffer, branch prediction, speculative execution and exceptions. We propose a systematic approach called the Completion Functions Approach to decompose and incrementally build its proof of correctness. The central idea is to construct the abstraction function using completion functions, one per unfinished instruction, each of which specifies the effect on the programmer visible state components of completing the instruction. This construction of the abstraction function leads to a very natural decomposition of the proof into proving a series of verification conditions. The approach prescribes a systematic way to generate these verification conditions which can then be discharged with a high degree of automation using techniques based on decision procedures and rewriting. The verification was completed in 34 person days, which we believe, is a modest investment in return for the significant benefits of formal verification.
Starting Page	171
Ending Page	213
Page Count	43
File Format	PDF
ISSN	09259856
Journal	Formal Methods in System Design
Volume Number	23
Issue Number	2
e-ISSN	15728102
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2003-01-01
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Software Engineering/Programming and Operating Systems Computer-Aided Engineering (CAD, CAE) and Design Electronic and Computer Engineering Circuits and Systems
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Software Hardware and Architecture

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