NDLI: Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS

Content Provider	SpringerLink
Author	Chen, Kairang Harikumar, Prakash Alvandpour, Atila
Copyright Year	2015
Abstract	This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB >12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.
Starting Page	87
Ending Page	98
Page Count	12
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	86
Issue Number	1
e-ISSN	15731979
Language	English
Publisher	Springer US
Publisher Date	2015-10-18
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Pipelined SAR ADC High resolution OTA Capacitive DAC Circuits and Systems Electrical Engineering Signal, Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

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