NDLI: A highly linear 1.2 V 12bit 5–45 MS/s CMOS pipelined ADC with CM-sensing-and-input-interchanged OTA sharing

Content Provider	SpringerLink
Author	Qin, Yajie Chen, Qihui Hong, Zhiliang Signell, Svante R.
Copyright Year	2012
Abstract	A 1.2 V 12bit programmable pipelined ADC is presented and implemented in 0.13 μm CMOS technology. A common-mode-sensing-and-input-interchanged OTA-sharing technique is proposed to address the non-resetting and successive-stage crosstalk issues in conventional OTA-sharing technique. Speed options of 5–45 MS/s are available with scalable power obtained by adjusting the bias currents for OTAs, comparators, and reference buffers, etc., or the global bias current. The measured signal-to-distortion-and-noise ratio is in range of 62.5–69.2 dB, and the peak spurious free dynamic range is 80.7 dB for all speed options, while the figure-of-merit is in the range of 0.26–0.49 pJ/conversion. The core area is 1.5 mm2.
Starting Page	237
Ending Page	241
Page Count	5
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	72
Issue Number	1
e-ISSN	15731979
Language	English
Publisher	Springer US
Publisher Date	2012-01-22
Publisher Place	Boston
Access Restriction	Subscribed
Subject Keyword	Pipelined ADC OTA sharing CM-sensing-and-input-interchanged Programmable Circuits and Systems Electrical Engineering Signal, Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

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A highly linear 1.2 V 12bit 5–45 MS/s CMOS pipelined ADC with CM-sensing-and-input-interchanged OTA sharing