NDLI: Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Content Provider	Springer Nature Link
Author	José, Wilson M. Silva, Ana Rita Véstias, Mário P. Neto, Horácio C.
Copyright Year	2014
Abstract	Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm2 integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm2 chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.
Starting Page	147
Ending Page	158
Page Count	12
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	82
Issue Number	1
e-ISSN	15731979
Language	English
Publisher	Springer US
Publisher Date	2014-12-04
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Matrix multiplication Many-core High-performance Algorithm-oriented design Application-specific integrated circuit Circuits and Systems Electrical Engineering Signal, Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Layout-Specific Circuit Evaluation in 3-D Integrated Circuits

Vestibular prosthesis design for restoring balance

High-Speed CMOS Track/Hold Circuit Design

An energy-efficient spike encoding circuit for speech edge detection

Design Approaches to Field-Programmable Analog Integrated Circuits

A Smart Sensor Integrated Circuit for NASA's New Millennium Spacecraft

Design and realization of a universal capacitive readout integrated circuit

A design-oriented methodology for accurate modeling of on-chip interconnects

Smart Power Integrated Circuit for a Piezoelectric Miniature Robot

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Similar Documents

Layout-Specific Circuit Evaluation in 3-D Integrated Circuits

Vestibular prosthesis design for restoring balance

High-Speed CMOS Track/Hold Circuit Design

An energy-efficient spike encoding circuit for speech edge detection

Design Approaches to Field-Programmable Analog Integrated Circuits

A Smart Sensor Integrated Circuit for NASA's New Millennium Spacecraft

Design and realization of a universal capacitive readout integrated circuit

A design-oriented methodology for accurate modeling of on-chip interconnects

Smart Power Integrated Circuit for a Piezoelectric Miniature Robot

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication