NDLI: Accurate delay models of CMOS CML circuits for design optimization

Content Provider	Springer Nature Link
Author	Jang, Ikchan Kim, Jintae Kim, SoYoung
Copyright Year	2014
Abstract	This paper presents accurate delay models of current-mode logic (CML) circuits for equation-based circuit optimization. We propose accurate edge-rate-dependent delay models of a CML buffer, a latch, and a multiplexer. Newly proposed delay models have compatibility with geometric programming and scalability for the hierarchical design of CML-based circuits, thereby enabling true constraint-driven equation-based design optimization. In order to validate these models, we show the modeling errors of unit CML gates over a wide range of delay and edge rates. N-stage CML buffers and a 28 Gb/s serializer in 45 nm CMOS technology are optimized for minimum power dissipation. The numerical experiments indicates that the proposed delay models can guarantee the intended operation of CML-based circuits when used in the equation-based design optimization.
Starting Page	297
Ending Page	307
Page Count	11
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	82
Issue Number	1
e-ISSN	15731979
Language	English
Publisher	Springer US
Publisher Date	2014-12-05
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	CMOS Current-mode logic gates Delay model Geometric programming Serializer Circuits and Systems Electrical Engineering Signal, Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

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