NDLI: A multisampling time-domain CMOS imager with synchronous readout circuit

Content Provider	Springer Nature Link
Author	Campos, Fernando S. Mariv, Ognian Faramarzpour, Naser Saffih, Fayçal Deen, M. Jamal Swart, Jacobus W.
Copyright Year	2008
Abstract	A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The proposed multisampling architecture requires only a single bit per pixel memory instead of 8 bits which is typical for time-domain active pixel architectures. The goal is to obtain a time-domain imager with high dynamic range that requires lower number of transistors per pixel in order to achieve higher fill-factor. The maximum frame rate is analyzed as a function of number of bits and array size. The analysis shows that it is possible to achieve high frame rates and operate in video mode having 10 bit pixel data resolution. Also, we present analysis of the impact of comparator offset voltage on the fixed pattern noise. The architecture was implemented in an imager prototype with 32 × 32 pixel array fabricated in AMS CMOS 0.35 μm and was characterized for sensitivity, noise and color response. The pixel size is 30 μm × 26 μm and it is composed of an n+/psub photodiode, a comparator and a D flip-flop with a 16% fill-factor.
Starting Page	151
Ending Page	159
Page Count	9
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	57
Issue Number	1-2
e-ISSN	15731979
Language	English
Publisher	Springer US
Publisher Date	2008-07-17
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Active pixel sensor Dynamic range Fill-factor CMOS imager Signal, Image and Speech Processing Electronic and Computer Engineering Circuits and Systems
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

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