NDLI: Analog to digital converter for high density neural signal recording front-end in 90 nm

Content Provider	Springer Nature Link
Author	Zarifi, Mohammad Hossein Farshchi, Shahin Frounchi, Javad
Copyright Year	2011
Abstract	High-fidelity recording of neural signals requires varying levels of signal gain to capture low-amplitude single-unit activity in the presence of high-amplitude population activity. A floating-point approach has been used to widen the dynamic range of analog-to-digital converters (ADC) designed for this application. In this paper we present an ADC, designed for multi-channel, portable neural signal recording systems. To achieve low power consumption, small die area and wide dynamic range, an ADC based on a time-based algorithm, combined with a floating-point pipelined structure has been designed and simulated. A conventional variable-gain amplifier (VGA) stage has been eliminated in favor of a reference-current in a time-based ADC architecture. The 12-b pipelined time-based floating-point ADC has been designed with a 7-b mantissa and an exponent that provides an additional 5 bits of dynamic range. The mantissa is determined by a uniform 7-b pipelined time-based analog to digital converter. The ADC chip was designed and simulated in a 90 nm CMOS process, which occupies an active area of 360 μm × 550 μm, and consumes 7.8 μW at 1.2 V in full-scale conversion.
Starting Page	349
Ending Page	355
Page Count	7
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	68
Issue Number	3
e-ISSN	15731979
Language	English
Publisher	Springer US
Publisher Date	2011-02-15
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Time-based ADC Floating-point ADC Pipeline ADC High speed latch comparator Offset cancellation Variable gain amplifier Implantable systems Signal, Image and Speech Processing Circuits and Systems Electrical Engineering
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An improved low offset latch comparator for high-speed ADCs

Reduced comparator high speed low power ADC using 90 nm CMOS technology

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

Implantable Neural Recording Front-Ends for Closed-Loop Neuromodulation Systems

A 10-b 120-MS/s 45 nm CMOS ADC using a re-configurable three-stage switched amplifier

A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters

Experimental evaluation of computer-controlled variable gain analog amplifiers

A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS

Differential Hot Electron Injection in an Adaptive Floating Gate Comparator

Analog to digital converter for high density neural signal recording front-end in 90 nm

Similar Documents

An improved low offset latch comparator for high-speed ADCs

Reduced comparator high speed low power ADC using 90 nm CMOS technology

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

Implantable Neural Recording Front-Ends for Closed-Loop Neuromodulation Systems

A 10-b 120-MS/s 45 nm CMOS ADC using a re-configurable three-stage switched amplifier

A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters

Experimental evaluation of computer-controlled variable gain analog amplifiers

A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS

Differential Hot Electron Injection in an Adaptive Floating Gate Comparator

Analog to digital converter for high density neural signal recording front-end in 90 nm