NDLI: Low-power CMOS distributed amplifier using new cascade gain cell for high and low gain modes

Content Provider	Springer Nature Link
Author	Farzamiyan, Amir Hossein Hakimi, Ahmad
Copyright Year	2012
Abstract	A CMOS distributed amplifier (DA) with low-power and flat and high power gain (S21) is presented. In order to decrease noise figure (NF) an RL terminating network used for the gate transmission line instead of single resistance. Besides, a flat and high S21 is achieved by using the proposed cascade gain cell consist of a cascode-stage with bandwidth extension capacitor. In the high-gain mode, under operation condition of V dd = 1.2 V and the overall current consumption of 7.8 mA, simulation result shown that the DA consumed 9.4 mW and achieved a flat and high S21 of 20.5 ± 0.5 dB with an average NF of 6.5 dB over the 11 GHz band of interest, one of the best reported flat gain performances for a CMOS UWB DA. In the low-gain mode, the DA achieved average S21 of 15.5 ± 0.25 dB and an average NF of 6.6 dB with low power consumption (PDC) of 3.6 mW, the lowest PDC ever reported for a CMOS DA or LNA with an average gain better than 10 dB.
Starting Page	453
Ending Page	460
Page Count	8
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	74
Issue Number	2
e-ISSN	15731979
Language	English
Publisher	Springer US
Publisher Date	2012-11-30
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	CMOS Distributed amplifier Cascade High gain Low power Circuits and Systems Electrical Engineering Signal, Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

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