NDLI: An integrated 10 GHz low-noise phase-locked loop with improved PVT tolerance

Content Provider	Springer Nature Link
Author	Hu, Kai Osmany, Sabbir A. Scheytt, J. Christoph Herzel, Frank
Copyright Year	2011
Abstract	An integrated phase-locked loop (PLL) with low phase noise is presented, which is robust with respect to variations of device parameters with process, supply voltage, and temperature (PVT). The low-noise CMOS voltage-controlled oscillator (VCO) employs two varactors for fine and coarse tuning. By using a CMOS charge pump with output biasing, the dc fine tuning voltage of the VCO and the loop dynamics of the PLL are well defined and fairly independent of PVT variations. Device noise in the charge pump and linearity of the phase detector are much improved by a two-transistor charge pump architecture for fine tuning. We measured a phase noise below −131 dBc/Hz at 10 MHz offset and below −94 dBc/Hz at 10 kHz offset over a tuning range of 1.2 GHz. An integrated phase error below 0.6° was measured, corresponding to an rms jitter below 160 fs. The chip was produced in a 0.25 μm low-cost SiGe BiCMOS technology, occupies a chip area of 2.25 mm2 and draws 60 mA from a 3 V supply.
Starting Page	319
Ending Page	330
Page Count	12
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	67
Issue Number	3
e-ISSN	15731979
Language	English
Publisher	Springer US
Publisher Date	2011-03-20
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Phase-locked loop Frequency synthesizer Phase noise Charge pump Satellite communications CMOS BiCMOS PVT tolerance Circuits and Systems Electrical Engineering Signal, Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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