NDLI: Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN

Content Provider	Springer Nature Link
Author	Mathew, J. Maharatna, K. Jose, B. R. Rahaman, H. Pradhan, D. K.
Copyright Year	2011
Abstract	An optimal implementation of 128-Pt FFT/IFFT for low power IEEE 802.15.3a WPAN using pseudo-parallel datapath structure is presented, where the 128-Pt FFT is devolved into 8-Pt and 16-Pt FFTs and then once again by devolving the 16-Pt FFT into 4×4 and 2×8. We analyze 128-Pt FFT/IFFT architecture for various pseudo-parallel 8-Pt and 16-Pt FFTs and an optimum datapath architecture is explored. It is suggested that there exists an optimum degree of parallelism for the given algorithm. The analysis demonstrated that with a modest increase in area one can achieve significant reduction in power. The proposed architectures complete one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 128-point FFT computation in less than 312.5 ns and thereby meet the standard specification. The relative merits and demerits of these architectures have been analyzed from the algorithm as well as implementation point of view. Detailed power analysis of each of the architectures with a different number of data paths at block level is described. We found that from power perspective the architecture with eight datapaths is optimum. The core power consumption with optimum case is 60.6 MW which is only less than half of the latest reported 128-point FFT design in 0.18u technology. Furthermore, a Single Event Upset (SEU) tolerant scheme for registers is also explored. The SEU tolerant scheme will not affect the performance, however, there is an increase power consumption of about 42 percent. Apart from the low power consumption, the advantages of the proposed architectures include reduced hardware complexity, regular data flow and simple counter based control.
Starting Page	871
Ending Page	882
Page Count	12
File Format	PDF
ISSN	0278081X
Journal	Circuits, Systems, and Signal Processing
Volume Number	30
Issue Number	4
e-ISSN	15315878
Language	English
Publisher	SP Birkhäuser Verlag Boston
Publisher Date	2011-05-17
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	FFT Low power System on chip WPAN Single event upset Electronics and Microelectronics, Instrumentation Electrical Engineering Signal, Image and Speech Processing Circuits and Systems
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Signal Processing

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