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DesignCon 2002 System-on-Chip and IP Design Conference Co-Verification : From Tool to Methodology
| Content Provider | Semantic Scholar |
|---|---|
| Author | Bailey, Brian |
| Copyright Year | 2002 |
| Abstract | While many design organizations are using HW/SW co-verification as a tool in their verification flow today, few have yet to make it an integral part of their complete methodology. With software becoming a more significant part of end designs in terms of its size, complexity, and ability to competitively differentiate a hardware platform, a verification strategy that includes both the hardware and software components is becoming essential. Additionally, verification environments are incorporating a wider range and combination of execution environments -such as event-based simulation, cycle-based simulation, emulation, co-simulation, etc. – including accommodation of their varying performance levels. This paper will discuss some of the tradeoffs made when setting up such environments and how these environments have been used in industrial cases. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://brianbailey.us/DC-SC20_Bailey.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
