Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs (1999)

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High Bandwidth, Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs

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Dynamically variable line-size cache exploiting high on-chip memory bandwidth of merged dram/logic lsis (1999).

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High Bandwidth, Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs (1998)

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A high-performance/low-power on-chip memory-path architecture with variable cache-line size.

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Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs

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Dynamically Variable Line-Size Caches Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs (1999)

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Dynamically variable line-size cache architecture for merged dram/logic lsis (2000).

Optimizing the DRAM refresh count for merged DRAM/logic LSIs

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