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Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
| Content Provider | Semantic Scholar |
|---|---|
| Author | Inoue, Koji Kai, Koji Murakami, Kazuaki |
| Copyright Year | 2000 |
| Abstract | SUMMARY This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called “dynamically variable line-size cache (D-VLS cache).” The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth on merged DRAM/logic LSIs appropriately. In our evaluation, it is observed that an average memory-access time improvement achieved by a directmapped D-VLS cache is about 20% compared to a conventional direct-mapped cache with fixed 32-byte lines. This performance improvement is better than that of a doubled-size conventional direct-mapped cache ∗ . |
| Starting Page | 1048 |
| Ending Page | 1057 |
| Page Count | 10 |
| File Format | PDF HTM / HTML |
| Volume Number | 83 |
| Alternate Webpage(s) | http://search.ieice.org/2000/pdf/e83-d_5_1048.pdf |
| Alternate Webpage(s) | https://catalog.lib.kyushu-u.ac.jp/opac_download_md/7348/Inoue3.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
