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Desenvolvimento de uma arquitetura reconfigurável para o processamento de modelos no ambiente ABACUS
| Content Provider | Semantic Scholar |
|---|---|
| Author | Lima, Verônica Aparecida Lopes |
| Copyright Year | 2007 |
| Abstract | The aim of this work is the development of a statically reconfigurable architecture, of a processing element (MPH) for the ABACUS circuit simulation environment. This processing element consists of a set of functional units that can be related by means of some control words stored in the ROM, and whose interconnection can be modified so that the processing hardware be adapted to the model of the circuit element to be simulated. The project was described in VHDL, and simulated with the aid of Quartus II software. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.feis.unesp.br/Home/departamentos/engenhariaeletrica/pos-graduacao/203-dissertacao_veronica_aparecida_lopes_lima.pdf |
| Alternate Webpage(s) | https://repositorio.unesp.br/bitstream/handle/11449/87216/lima_val_me_ilha.pdf?isAllowed=y&sequence=1 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
