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Implementation of Asynchronous pipeline Using Verilog HDL
| Content Provider | Semantic Scholar |
|---|---|
| Author | Lakshmi, G. Vijaya Srinivasarao Addagalla Ramana, B. Venkat |
| Copyright Year | 2016 |
| Abstract | The asynchronous paradigm has interesting features due to the lack of the clock signal and it is another option for the project of digital systems. This paradigm has several design styles, where the micropipeline style is the most suitable one for FPGA platforms, due to the simplicity of its control. In this paper, we propose a pipeline architecture to implement asynchronous digital systems, in bundled-data micropipeline style. In this architecture we are MOUSTRAP architecture. By using this architecture we can reduce the delay as well as we can reduce the power. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ijcsiet.com/pdf/01112015-003.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
