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Multiple-valued Logic in FPGAs
| Content Provider | Semantic Scholar |
|---|---|
| Author | Zilic, Zeljko |
| Copyright Year | 1993 |
| Abstract | This paper considers the applicability of multiple-valued logic (MVL) circuits in implementation of field-programmable gate arrays (FPGAs). I t proposes an FPGA logic block architecture that features MVL current-mode CMOS circuitry. The logic block combines the lookup-table and multiplexer approaches found in FpGAs, and provides versatility through its current-mode operation. Its main purpose is to motivate future work in this direction, by discussing the feasibility of MVL logic blocks and their impact on the architecture of FPGAs. 2.0 Current-Mode MVL Circuits Recent experience shows that current-mode circuits are attractive for implementation of MVL functions. Most of the circuits and synthesis techniques in the literature have been intended for the 4-valued (quartemary) environment [2], [7]. Current-mode circuits offer several advantages, 1 .O Introduction Field Programmable Gate Arrays (FPGAs) are rapidly becoming a popular choice for implementation of digital circuits where quick turn-around time and low cost are important considerations. They are replacing the more traditional application-specific integrated circuits (ASICs) in a growing number of applications. The disadvantages of FPGAs are primarily due to lower density and speed, in comparison with ASICs and mask-programmable gate arrays. Both speed and density in FPGAs are affected by the structure of the logic blocks and the interconnect between them. The interconnect is of particular importance because it can occupy as much as 75 percent of the chip area [ 13, [4]. While all existing FPGAs are based on binary circuits, it is interesting to consider the possibility of using multiple-valued logic (MVL) circuits instead. In particular, it may be attractive to use current-mode CMOS technology for this purpose. Current-mode circuits may result in significant speed improvements, while the use of MVL signals may reduce the size of the interconnect. A recent study gives an example of improved speed in the case of a typical SRAM bit-line, where a delay was found to be 5 ns for conventional voltage-mode operation and less than 0.3 ns for current-mode signals [8]. but they also have some disadvantages. Perhaps the most important advantage is the ease of summation of signals, while the main difficulty lies in the signal distribution limitations caused by the natural fanout being equal to one. In practice, it is useful to augment the current-mode circuits with some intermediate voltage-mode circuits, which often results in more effective designs. Figure 1 gives the basic blocks used in our design. All of these blocks have been used before [2], [7], [9]. Here, we will only summarize their characteristics. Currents are summed by means of a simple wired connection. Current sources are realized as an N-type or a P-type transistor with the gate connected to a reference voltage. The amount (value) of current is proportional to the ratio of W/L. Signal distribution can be performed using current mirrors, which can be of either N-type or P-type. We will use both types. The current produced at the output is determined by the input current and the ratio of the W/L values of output and input transistors. In addition to signal distribution, the current mirror can be used for multiplication with a constant and for sign reversal. A threshold detector block takes a multiple-valued input current signal and produces a voltage signal. The output signal is High if the input exceeds a predefined reference value; otherwise the output signal is Low. Threshold detectors generate signals that can be used with normal binary logic gates and for control of pass-transistor networks. Apass transistor is a voltage-conkolled device, which enables or disables the This paper presents an attempt to investigate the possibility of exploiting MVL circuits in the FPGA environment. CH 3381-11931$01.00 01993 IEEE 1553 current flow, depending on the gate voltage. We will use both N and P-type pass transistors. FIGURE 1. Basic Current Mode Blocks L.oe.ExDressioo I Symbol I Circuil Realizalion |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.eecg.toronto.edu/~zeljko/CurFPGA.ps.Z |
| Alternate Webpage(s) | http://iml.ece.mcgill.ca/people/professors/zilic/documents/mvlfpga.pdf |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | Application-specific integrated circuit Basic block CMOS Comparator applications Converter Device Component Current mirror Current source Detectors Digital electronics Electronic circuit Fan-out Field-programmability Field-programmable gate array Inferring horizontal gene transfer Logic block Logic gate Lookup table Multiple Myeloma Multiple Personality Disorder Multiplexer Multiplication Static random-access memory Transistor Transistors voltage |
| Content Type | Text |
| Resource Type | Article |
