NDLI: Quaternary Logic Lookup Table in Standard CMOS

Content Provider	IEEE Xplore Digital Library
Author	Brito, D. Rabuske, T.G. Fernandes, J.R. Flores, P. Monteiro, J.
Copyright Year	1993
Abstract	Interconnections are increasingly the dominant contributor to delay, area and energy consumption in CMOS digital circuits. Multiple-valued logic can decrease the average power required for level transitions and reduces the number of required interconnections, hence also reducing the impact of interconnections on overall energy consumption. In this paper, we propose a quaternary lookup table (LUT) structure, designed to replace or complement binary LUTs in field programmable gate arrays. The circuit is compatible with standard CMOS processes, with a single voltage supply and employing only simple voltagemode structures. A clock boosting technique is used to optimize the switches resistance and power consumption. The proposed implementation overcomes several limitations found in previous quaternary implementations published so far, such as the need for special features in the CMOS process or power-hungry current-mode cells. We present a full adder prototype based on the designed LUT, fabricated in a standard 130-nm CMOS technology, able to work at 100 MHz while consuming 122 μW. The experimental results demonstrate the correct quaternary operation and confirm the power efficiency of the proposed design.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	306
Ending Page	316
Page Count	11
File Size	5143346
File Format	PDF
ISSN	10638210
Volume Number	23
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Table lookup Transistors CMOS integrated circuits Capacitance Multiplexing Switches standard CMOS technology. Field-programmable gate array (FPGA) lookup table (LUT) multiple-valued logic (MVL) quaternary logic standard CMOS technology
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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