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Register Assignment for Architectures with Partitioned Register Banks
| Content Provider | Semantic Scholar |
|---|---|
| Author | Hiser, Jason Carr, Steve Sweany, Philip H. |
| Abstract | With aggressive instruction scheduling techniques and significant increases in instruction-level parallelism (ILP), modern computer architectures have seen an impressive increase in performance. Unfortunately, large amounts of ILP hardware and aggressive instruction scheduling techniques put large demands on a machine’s register resources. With these demands, it becomes difficult to maintain a single monolithic register bank. The number of ports required for such a register bank severely hampers access time [3, 9]. Partitioned register banks are one mechanism for providing high degrees of ILP with a high clock rate (Texas Instruments already produces several DSP chips that have partitioned register banks to support high ILP [16].) Unfortunately, partitioned register banks may inhibit achieved ILP. An instruction may be able to be scheduled in a particular cycle, but if its data resides in a register bank that is not accessible to the available functional unit, extra instructions must be inserted to move the data to the register bank of an available functional unit in order to allow execution. Therefore, a compiler must deal not only with achieving maximal parallelism via aggressive scheduling, but also with data placement among a set of register banks. So, a compiler for an ILP architecture with partitioned register banks must decide, for each operation, not only where the operation fits in an instruction schedule, but also in which register partition(s) |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://m.mtu.edu/cs/research/papers/pdfs/total.pdf |
| Alternate Webpage(s) | http://www.cs.mtu.edu/html/tr/99/9901/total.pdf |
| Alternate Webpage(s) | http://www.mtu.edu/cs/research/papers/pdfs/total.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
