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Cache Performance , System Performance , and Off-Chip Bandwidth . . . Pick any Two
| Content Provider | Semantic Scholar |
|---|---|
| Author | Ahsan, Bushra |
| Abstract | One of the major challenges NoC and on-board interconnection has to face in current and future multicore chips is the skyrocketing off-chip bandwidth requirement. As the number of cores increases, the demand for off-chip bus, memory ports, and chip pins increases and this can severely hurt performance. It leads to bus congestion, processor stalls and hence, performance loss. Off-chip bandwidth is generated by the on-chip cache hierarchy (cache misses and cache writebacks). This paper studies the interaction among off-chip bandwidth requirement, cache performance, and overall system performance in multicore systems. The traffic from the chip to the memory is due to the writes which are sent from the last level on-chip cache to the memory, or to the following level external cache, whenever a block is replaced from the cache. We relax some constraints of the well known LRU replacement policy. We call it Modified Least Recently Used (MLRU) policy which essentially reduces the traffic from the chip to the memory system. Simulations using the MLRU policy show considerable writeback decrease by more than 90% with a minimum performance impact. However, it shows also some interesting interaction among cache performance, overall system performance, and off-chip writeback traffic. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.mzahran.com/ina-ocmc09.pdf |
| Alternate Webpage(s) | http://www-ee.ccny.cuny.edu/www/web/mzahran/ina-ocmc09.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
