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Dummy Gate-Assisted n-MOSFET Layout for a Radiation-Tolerant Integrated Circuit
| Content Provider | Semantic Scholar |
|---|---|
| Author | Lee, Hee Chul |
| Copyright Year | 2013 |
| Abstract | A dummy gate-assisted n-type metal oxide semiconductor field effect transistor (DGA n-MOSFET) layout was evaluated to demonstrate its effectiveness at mitigating radiation-induced leakage currents in a conventional n-MOSFET. In the proposed DGA n-MOSFET layout, radiation-induced leakage currents are settled by isolating both the source and drain from the sidewall oxides using a p+ layer and dummy gates. Moreover, the dummy gates and dummy Metal-1 layers are expected to suppress the charge trapping in the sidewall oxides. The inherent structure of the DGA n-MOSFET supplements the drawbacks of the enclosed layout transistor, which is also proposed in order to improve radiation tolerance characteristics. The Vg-Id simulation results of the DGA n-MOSFET layout demonstrated the effectiveness of eliminating such radiation-induced leakage current paths. Furthermore, the radiation exposure experimental results obtained with the fabricated DGA n-MOSFET layout also exhibited good performance with regard to the total ionizing dose tolerance. |
| Starting Page | 3084 |
| Ending Page | 3091 |
| Page Count | 8 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/TNS.2013.2268390 |
| Volume Number | 60 |
| Alternate Webpage(s) | http://tarjomefa.com/wp-content/uploads/2017/09/7783-English-TarjomeFa.pdf |
| Alternate Webpage(s) | https://doi.org/10.1109/TNS.2013.2268390 |
| Journal | IEEE Transactions on Nuclear Science |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
