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Applications of a Bit-serial Floating-point Complex Multiplier-accumulator for High-speed Digital Signal Processing
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 2004 |
| Abstract | This paper deals with the problem of building compact, highspeed, fault-tolerant digital signal processors which utilize the bit-serial floating-point complex multiplier-accumulator (CMAC) as a processing element. Two target applications will be described in this paper the Fast Fourier Transform (FFT) and the block least mean square (BLMS) adaptive finite impulse response (FIR) filter. The present study is intended as a starting point whereby the features implemented in the CMAC can be used in the design of other types of processing elements, and these will serve as a library of macrocells from which advanced digital signal processors can be constructed with fast turnaround time. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://www.computer.org/csdl/proceedings/acssc/1988/9999/02/00754616.pdf |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | Accumulator (computing) Accumulator Device Component Central processing unit Digital signal processing Digital signal processor Fast Fourier transform Fault tolerance Finite impulse response Float Mean squared error Multiply–accumulate operation One-key MAC Serial communication |
| Content Type | Text |
| Resource Type | Article |
