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Highly accelerated advanced multiplier design for an efficient bandwidth utilized fft computation.
| Content Provider | CiteSeerX |
|---|---|
| Author | Sahithi, M. Shaik, Naseema Rani, A. Jhansi Poornima, J. Jyothi, M. Purnima, K. |
| Abstract | Abstract — Fast multipliers are essential parts of digital signal processing systems. The speed of multiply operation is of great importance in digital signal processing as well as in general purpose processors today especially since the media processing took off. We present a Fast fourier transform implementation using Twin precision technique. The twin precision technique can reduce the power dissipation by adapting a multiplier to the bit width of the operands being computed. The algorithm used here is Baugh-Wooley algorithm. By adapting to actual multiplication bit-width using twin precision technique, it is possible to save power, increase speed, double computation throughput and highly efficient. By using this the execution time of a Fast fourier transform is reduced with 15 % at a 14% reduction in datapath energy dissipation. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Twin Precision Technique Accelerated Advanced Multiplier Design Efficient Bandwidth Utilized Fft Computation Increase Speed Baugh-wooley Algorithm Double Computation Throughput Essential Part Datapath Energy Dissipation Fast Fourier Transform Great Importance Digital Signal Processing System Actual Multiplication Bit-width Abstract Fast Multiplier Bit Width Multiply Operation Power Dissipation General Purpose Processor Today Fast Fourier Transform Implementation Execution Time Digital Signal Processing |
| Content Type | Text |
