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Implications of CPU Caching on Byte-addressable Non-Volatile Memory Programming
| Content Provider | Semantic Scholar |
|---|---|
| Author | Bhandari, Kumud Chakrabarti, Dhruva R. |
| Copyright Year | 2012 |
| Abstract | Byte-addressable non-volatile memory may usher in a new era of computing where in-memory data structures are persistent and can be reused directly across machine restarts. However, sudden failures complicate matters because a program state may partially reside in volatile buffers and caches as opposed to primary non-volatile memory. We study the implications of different CPU caching modes and show that a particular choice affects both programmability and performance of a program. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.hpl.hp.com/techreports/2012/HPL-2012-236.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
