Loading...
Please wait, while we are loading the content...
Similar Documents
Redesigning Data Structures for Non-Volatile Byte-Addressable Memory
| Content Provider | Semantic Scholar |
|---|---|
| Author | Venkataraman, Shivaram Tolia, Niraj H. Ranganathan, Parthasarathy Campbell, Roy H. |
| Copyright Year | 2010 |
| Abstract | Recent architecture trends show that DRAM density scaling is facing significant challenges and will hit a scalability wall at 40nm [4, 5]. Additionally, power constraints will also limit the amount of DRAM installed in future systems [3]. To support next generation systems, technologies such as Phase Change Memory (PCM) and Memristor are being developed as DRAM replacements. These memories offer latencies that are orders of magnitude lower than either disk or flash and are comparable to DRAM. Not only are they byte-addressable like DRAM but, in addition, they are non-volatile. Projected cost analysis [3] and power-efficiency characteristics of Non-Volatile Byte-addressable Memory (NVBM) lead us to believe that it can replace both disk and memory in data stores (e.g., databases, NoSQL systems, etc.) but not through legacy block or file systems interfaces. The overhead of these interfaces will dominate NVBM’s nanosecond access latencies and furthermore, these interfaces impose a two-level logical separation of data, differentiating between in-memory vs. on-disk copies of data. Traditional data stores have to both update the in-memory data and, for durability, sync the data to disk with the help of a write-ahead log. Not only does this data movement use extra power and reduce performance for low latency NVBM, the logical separation also reduces the capacity of an NVBM system. Instead, we propose a single-level NVBM hierarchy where no distinction is made between a volatile and a persistent copy of data. With a single-level NVBM store, we need to ensure that data structures will never be left in an inconsistent state. Unfortunately, processors today do not provide the necessary extensions to prevent writes from being flushed from cache to memory and given that the memory controller can reorder cache line writes, current mechanisms for updating data structures are likely to cause corruption in the face of failures. To address the above requirements for NVBM, we propose the use of Consistent and Durable Data Structures (CDDSs), a design that allows for the creation of log-less storage systems on non-volatile memory without processor modifications. These data structures allow mutations to be safely performed directly (using loads and stores) on the single copy of data. Instead of using write-ahead logging or shadow paging, we have architected CDDSs to use 10 [6,-) 20 [6,-) 99 [6,-) |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://tolia.org/files/pubs/nvmw2011.pdf |
| Alternate Webpage(s) | http://www.tolia.org/files/pubs/nvmw2011.pdf |
| Alternate Webpage(s) | http://shivaram.org/publications/nvm-nvmw11.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
