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Design and Implementation of Router for NOC on FPGA
| Content Provider | Semantic Scholar |
|---|---|
| Author | Verma, Gaurav Agarwal, Harsh Singh, Shreya Khanam, S. Gupta, Prateek Kumar Jain, Vishal |
| Copyright Year | 2016 |
| Abstract | In today’s technological era, SOC has undergone rapid evolution and is still processing at a swift pace. But due to this explosive evolution of semiconductor industry, the devices are scaling down at a rapid rate and hence, SOC today have become communication-centric. However, the existing bus architectures comprising of wires for global interconnection in SOC design are undergoing design crises as they are not able to keep up with the rate of scaling down of devices. To overcome bottleneck of communication system, NOC is an upcoming archetype. In on-chip network, router is considered as an important component. This paper proposes router, its components and parameters which affects the entire design. Thus, to validate the functioning of NOC on hardware, router has been designed in VHDL and simulated in Xilinx ISE 14.1 targeting Xilinx XC5VLX30-3 FPGA. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.sersc.org/journals/IJFGCN/vol9_no12/24.pdf |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | Anatomy, Regional Architecture as Topic Bronchiolitis Obliterans Call of Duty: Black Ops Clock signal Copyright Eurographics FIFO (computing and electronics) Field-programmable gate array Image scaling Interconnection Iontophoresis LL parser Lobular Neoplasia Local Interconnect Network MedDRA System Organ Class Mesh networking NOC - CodeSystem Network on a chip Round-robin scheduling Router (computing) Routing Semiconductor industry Still Processing Swift (programming language) System on a chip Test scaling VHDL Xilinx ISE cellular targeting |
| Content Type | Text |
| Resource Type | Article |
