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Design of NoC Router Architecture using VHDL
| Content Provider | CiteSeerX |
|---|---|
| Author | Wanjari, Minakshi M. Agrawal, Pankaj Kshirsagar, R. V. |
| Abstract | Network-on-Chip (NoC) is an advance design method of communication network into System-on-Chip (SoC). It provides solution to the problems of traditional bus-based SoC. It is widely considered that NoC will take the place of traditional bus-based design and will meet the communication requirements of next SoC design. A router is the key component and called as the communication backbone in NoC. This paper presents NoC router architecture which has low latency and requires less area. The design is implemented in VHDL and simulated in Xilinx ISE Design Suite 13.1. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Noc Router Architecture Xilinx Ise Design Suite Communication Network Communication Requirement Low Latency Communication Backbone Key Component Advance Design Method Traditional Bus-based Design Next Soc Design Traditional Bus-based Soc |
| Content Type | Text |
| Resource Type | Article |
