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Low power flip-flop with clock gating on master and slave latches
| Content Provider | Semantic Scholar |
|---|---|
| Author | Ag, Martynova |
| Copyright Year | 2004 |
| Abstract | I Conclusion: In this Letter, we have shown that the method proposed in [2] could be used even in the case where non-neglectible values of feedback delay are encountered. A very interesting conclusion is that an optimal gain margin may be reached with a nonzero value, i.e. a physical delay value. Furthermore, this delay (higher than one sampling period) allows for dynamic element matching techniques in the case of multibit modulators. Q |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.eng.auburn.edu/~agrawvd/COURSE/E6270_Fall07/PROJECT/LUO/Low%20power%20flip-flop%20with%20clock%20gating%20on%20master%20and%20slave%20latches.pdf |
| Alternate Webpage(s) | http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Fall07/PROJECT/LUO/Low%20power%20flip-flop%20with%20clock%20gating%20on%20master%20and%20slave%20latches.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
