Analysis of Modified Energy Recovery Flip Flops with Clock Gating

Content Provider	NIT Kurukshetra
Advisor	Gupta, Vrinda
Researcher	Kumar, Amit
Date Awarded	2013-07-01
Abstract	In recent years as the demand for portable consumer electronics products is highly increasing therefore development of low-power VLSI circuits is needed. The flip flops are the basic storage element in most of the digital electronics circuits like laptop, mobile, microprocessor, watch, washing machine, microwave, refrigerator etc. Therefore many innovative designs for flip flops have appeared. Low-power design is not only needed for portable applications but also to reduce the power of high-performance systems. For implementing these logic designs, various types of energy recovery flip flops are used which are most important components in digital design. The performance of these Energy Recovery Flip Flops can be measured in term of power dissipation at different clock frequency. In this dissertation, Modified energy recovery flip flops with clock gating namely single ended conditional capturing energy recovery (SCCER) flip-flop with clock gating; differential conditional capturing energy recovery (DCCER) flip flop with clock gating; static differential energy recovery (SDER) flip-flop with clock gating are proposed. In modified SCCER flip flop with clock gating, the gate of upper most transistor is connected to drain of same transistor to convert the pseudo NMOS logic to adiabatic logic to reduce the power of a conventional flip flop. In modified (DCCER) flip-flop with clock gating, that gate of upper PMOS transistors of conventional flip flop is connected to drain of the each other transistors to convert pseudo NMOS logic to adiabatic logic to reduce the power of a conventional flip flop. In modified SDER energy recovery flip flop with clock gating, evaluating transistors which are connected at output logic are removed to reduce the area and the power of conventional flip flop. The simulator being used is Mentor Graphics Design Architect with 180 nanometer technology. Here 180 nanometer means channel length. The supply voltage used in simulation work is 1.8Volt. Eldo and EZ wave were used for checking power and the waveform. According to simulations results, the Modified energy recovery flipflops reduces the power up to 20- 25% of the total power dissipation as compared to the conventional energy recovery flip-flops.
Page Count	62
File Format	PDF
Language	English
Publisher Department	Department of Electronics & Communication Engineering
Publisher Institution	National Institute of Technology, Kurukshetra
Publisher Place	Kurukshetra, Haryana
Access Restriction	Open
Subject Keyword	Clocking in Synchronous System Conventional Dccer Flip Flop Conventional Sccer Flip Flop Conventional Sder Flip Flop Disadvantages of Clock Gating Method Disadvantages of Conventional Flip Flops Drawbacks of Previous Work Dynamic Power Consumption Leakage Power Consumption Low Power Design Methodology Modified Dccer Flip Flop Modified Sccer Flip Flop Modified Sder Flip Flop Need of Low Power in Clock Gating Power Dissipation Power Dissipation in CMOS Short Circuited Power Dissipation Simulations, Results and Discussion Tools Used (Mentor Graphic Design Architect) Version Types of Energy Recovery Flip Flops
Content Type	Text
Educational Degree	Master of Technology (M.Tech.)
Resource Type	Thesis